1. Field of the Invention
This invention relates to a D/A converter that converts a digital signal to an analog signal and a liquid crystal display device provided with the D/A converter.
2. Description of the Related Art
In an active matrix type liquid crystal display device, when a video signal from a video source is a digital signal, the video signal has been converted from digital to analog with a D/A converter and applied to pixels to perform multi-gray scale display that corresponds to the number of bits of the digital signal.
FIG. 4 is a circuit diagram showing a conventional D/A converter. The D/A converter converts three bits of digital signals D0, D1 and D2 into an analog signal. A terminal of each of four capacitors C1, C2, C3 and C4 is grounded. The capacitors C1, C2, C3 and C4 have capacitances C, C, 2C and 4C, respectively. That is, each of the three capacitors C2, C3 and C4 is weighted according to a weight of each bit of the digital signals D0, D1 and D2, respectively. A selection circuit SEL selects and outputs either a first reference electric potential V1 or a second electric potential V2, according to a value of each bit of the digital signals D0, D1 and D2.
In response to a transfer pulse TP, a transfer transistor TT1 transfers the first reference electric potential V1 to an other terminal of the capacitor C1, while each of three transfer transistors TT2, TT3 and TT4 transfers corresponding output of the selection circuit SEL to an other terminal of corresponding each of the capacitors C2, C3 and C4, respectively. In response to a charge pulse CP, charge transistors CT2, CT3 and CT4 connect the other terminals of the four capacitors C1, C2, C3 and C4 with each other, and an output transistor CT1 outputs an analog signal determined by electric charges shared among the other terminals of the four capacitors C1, C2, C3 and C4 that are connected together in response to the charge pulse CP.
FIG. 5 is an operational timing chart of the D/A converter. When the digital signals D0, D1 and D2 are established, either the first reference electric potential V1 or the second reference electric potential V2 (V2>V1) is selected for each bit by the selection circuit SEL. After that, when the transfer pulse TP turns to an H level, the four transfer transistors TT1, TT2, TT3 and TT4 are turned on to charge the capacitors C1, C2, C3 and C4. After that, when the transfer pulse TP falls to an L level and the charge pulse CP rises to the H level, the other terminals of the capacitors C1, C2, C3 and C4 are connected together by the charge transistors CT2, CT3 and CT4 and the electric charges stored in the capacitors C1, C2, C3 and C4 are equally shared by the capacitors C1, C2, C3 and C4 to thereby determine an electric potential of the analog signal Vout. The analog signal Vout is outputted through the output transistor CT1.
Here, the analog signal Vout can be expressed by the following equation 1, according to the law of conservation of electric charge.
                    Vout        =                                                                                                                                                                          4                          ⁢                                                      C                            ⁡                                                          (                                                                                                V                                  ⁢                                                                                                                                          ⁢                                  1                                                                +                                                                                                      D                                    2                                                                    ⁡                                                                      (                                                                                                                  V                                        ⁢                                                                                                                                                                  ⁢                                        2                                                                            -                                                                              V                                        ⁢                                                                                                                                                                  ⁢                                        1                                                                                                              )                                                                                                                              )                                                                                                      +                                                                                                                                                                          2                          ⁢                          C                          ⁢                                                      (                                                                                          V                                ⁢                                                                                                                                  ⁢                                1                                                            +                                                                                                D                                  1                                                                ⁡                                                                  (                                                                                                            V                                      ⁢                                                                                                                                                          ⁢                                      2                                                                        -                                                                          V                                      ⁢                                                                                                                                                          ⁢                                      1                                                                                                        )                                                                                                                      )                                                                          +                                                                                                                                                                                      C                    ⁢                                          (                                                                        V                          ⁢                                                                                                          ⁢                          1                                                +                                                                              D                            0                                                    ⁡                                                      (                                                                                          V                                ⁢                                                                                                                                  ⁢                                2                                                            ⁢                                                                                                                          -                                                              V                                ⁢                                                                                                                                  ⁢                                1                                                                                      )                                                                                              )                                                        +                                      CV                    ⁢                                                                                  ⁢                    1                                                                                            8            ⁢            C                                              [                  Equation          ⁢                                          ⁢          1                ]            
A display device using this kind of D/A converter is disclosed in Japanese Patent Application Publication No. 2003-122326.
With the D/A converter described above, however, there has been a problem that the power consumption is large because the capacitors C2, C3 and C4 must be charged and discharged to the reference voltage corresponding to the values of the digital signals D0, D1 and D2 every time the digital signals D0, D1 and D2 change their values.